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dehrmann
on June 23, 2020
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TSMC officially begins 5 nm production
These days, are you more likely to have dead cores, reduced cache, or reduced clock speed for chips in low bins?
tyingq
on June 23, 2020
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If pictures like this are accurate, I assume cache problems would be the most likely:
https://i.stack.imgur.com/4Z1nU.png
aprao
on June 23, 2020
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Can you describe what I should be seeing here?
tyingq
on June 23, 2020
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root
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That most of the die area is L1/2/3 cache.
aprao
on June 23, 2020
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gotcha, thanks
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